1. Field of the Invention
The embodiments of the invention provide methods, systems, computer program products, etc. for incomplete write protection for a disk array.
2. Description of the Related Art
Software redundant array of independent (or inexpensive) disks (RAID) is becoming more popular. Recent desktop PC chipsets support various software RAID designs, such as RAID 5. However, battery backed cache is not generally available in motherboards based on these chipsets.
In RAID 5, one parity and a set of data disks is provided (ignoring parity rotation for now). The typical one element write is W(A2)→R(A1),R(P111); W(A2),W(P211); WC. The power loss in post-hard break write still causes inconsistent parity for the stripe. While the host knows W(A2) did not complete as an entire operation, it knows nothing of the state of P, which could be P111 or P211, or the data in A, which could be A1 or A2. Thus, if there is a subsequent disk failure, the data recovered into B1 or C1 may be corrupted due to the unknown state of the parity stripe. That is because P111=(A1+B1+C1), and P211=(A2+B1+C1) (here + means XOR), and B1 is recovered by B1=P+A+C1. This requires having P and A be consistent—either P111, A1, or P211, A2. If P111, A2 or P112, A1 is given, the data given for B is corrupt and there is no way of knowing. This is why parity RAID without battery-backed cache is risky, and why an invention is needed when such a cache is not available. Note it is termed a write cache, it doesn't have to be used as a write-back cache. A battery-backed buffer is also provided, since this problem occurs even without write-back caching enabled. Write-back caching is when WC is issued on receipt of W(A2) and there is a promise to complete the write at a later time. This speeds things up dramatically, but again requires battery backup. Referring now to FIG. 1A, a RAID stripe having one parity and a set of data disks is shown. FIG. 1B illustrates the stripe state after a power loss.